Design for Test (DFT) has gone in recent years from a somewhat beneficial feature to a necessity within integrated circuits. Originally focused on digital circuits with the inclusion of circuit elements for Built-In Self-Test (BIST), and subsequently expanding to Built-In Test Equipment (BITE), the DFT methodology has now penetrated all areas of electronics and IC design, but is especially important with increasing operational speeds and increased integration in analog and mixed signal circuits where demands for performance, reliability, and defectivity are increasing whilst customer continually demand decreasing costs and guaranteed supply.
The motivations to employ DFT strategies in IC design are not always obvious at the first glance. Implementing DFT into an IC typically results in add-on test circuitry, which does not improve the primary circuit functions. It does not make a circuit faster, it does not reduce the power consumption, and it does not make it more robust to variations of process or environmental parameters. Even worse, the circuitry for testing adds additional problems. Circuit performance may be degraded, if for example switching elements are added into signal paths. Chip complexity increases, and a particularly elegant circuit solution is often questionable after test circuitry has “ruined” the layout.
DFT strategies are not merely an add-on module to an existing, and working, circuit solution but dominantly shape the semiconductor circuit solution, by for example determining the module boundaries, bring limitations and restrictions to the freedom of the analog designer and of the circuit implementation, and require additional circuitry which increases the die area, therefore increasing the die manufacturing costs and increasing the probability of faults in the chip.
As such a driving force to utilize DFT for analog and mixed signal ICs comes from market demands identified previously. One main reason for DFT is to reduce the (final) costs of ICs through reducing testing time. Testing a mixed-signal chip after production is typically responsible for between 30% and 80% of the total cost, depending on chip system complexity, volume, and application demands. Furthermore, DFT increases the testability per definition and, therefore, increases the fault coverage, which in turn increases the reliability of a circuit in the field by reducing early life failures. This is particularly important where industry trends are to single figure part per million (ppm) failures.
Another main reason to employ DFT for ICs is the demands from safety critical, highly dependable, and high reliability applications. Complex solutions for the health, nuclear, or transportation industries including automotive, aerospace and public transportation applications demand high testability and on-line functional verification to allow safe, dependable and reliable operation. Furthermore, legislative requirements and demands from insurers in many cases necessitate proof of “completeness” in testing after manufacture and even continuing on-line verification capabilities for certain applications. As such DFT evolves from a mere idea to make the test engineers life easier to a concept which is paramount to successful IC design, production, marketing, and sales.
DFT techniques evolved primarily from the digital circuit domain, and the vast majority of DFT approaches exploit digital circuits to communicate with other circuitry, perform analysis, and are digital circuits themselves. However, with digital circuits routinely operating at 10 Gb/s and above in telecommunications and developments extending to 40 Gb/s and 100 Gb/s, the line between digital and analog signals is increasingly blurring. Analog signals are often considered to be continuous signals but today's systems can operate with multiple modulation formats, frequency agility, short aperiodic bursts and digital encoding. Hence, the original differentiations between analog and digital test equipment are disappearing and circuit designs at these high speeds and operating frequencies becoming more synergistic in building blocks, semiconductor technology and testing requirements.
Historically, the design of “analog” circuits has been one with significantly less design automation than digital circuits, and is further compounded by supporting multiple semiconductor technologies such as SiGe, GaAs, and InP rather than simply silicon. As such whilst an analog element of a mixed signal IC may take up only 5-10% of the die footprint it's design can take 80-90% of the development time and it's production testing a similar proportion of test time.
As a result there has been interest in expanding the overall embrace of DFT into circuits by expanding the BIST/BITE toolset with the inclusion of an on-chip oscilloscope function such that critical parameters such as rise-time, fall-time, eye-opening, jitter, and noise can be measured automatically in real-time within the circuit. Conventional automated test equipment (ATE) for high-speed characterization of signals has centered on digital oscilloscopes, and their closely related counterpart the logic analyzer. Prior art has addressed elements of reducing either the complexity or requirements of the ATE whilst beginning the first steps of integrating the required functionality into an IC.
Prior art has therefore tended to either mimic the design of conventional time-domain oscilloscopes or provide an interface to such conventional instruments. As such prior circuits providing the special focus on BITE have addressed the issue of sampling the high-speed signals with an integrated circuit block thereby allowing the signal integrity within a mixed signal IC to be evaluated. Such an approach was reported by Delmas Ben-Dhia et al; (S. Delmas Ben-Dhia et al, “On-Chip Sampling in CMOS Integrated Circuits” IEEE Trans. Of Elec. Comp. Vol. 41, No. 4, pp 403-406, November 1999), to evaluate CMOS circuits. This integrated sampling approach has been extended by Ho et al, (R. Ho et al; “Applications of On-Chip Samplers for Test and measurement of Integrated Circuits” Dig. IEEE Symposium of VLSI Circuits, pp 138-139, June 1998), where the sampling allowed the evaluation of the VLSI circuit with a lower speed external oscilloscope.
In fact, these prior art solutions sought to address the cost of automated test equipment by embedding the high speed sampling circuit within the VLSI IC, an SRAM in the case of Ho et al, and coupling this circuit block to conventional logic analyzer/oscilloscope units external to the IC. Digitization or analysis of the signal within the IC was performed externally to the IC in these prior art approaches. Typically, signal digitization in the prior art was undertaken using external analog buffers and analog-to-digital (ADC) circuits, generally within conventional laboratory test instruments.
A step further in integration from the sampling circuit is the provisioning of the measurement clock signals necessary to control the BITE circuitry. Such measurement clock signals having been at lower speeds than the IC clock signals in these prior art solutions which address repetitive high speed signals, but would need to be at higher speeds than the IC clock signals in real time, single shot characterization and evaluation circuits for DFT, especially in capturing error events and on-line real time analysis. Such on-chip clock generation was demonstrated in the prior art by Takamiya et al, (M. Takamiya et al, “An On-Chip 100 GHz Sampling Rate 8-Channel Sampling Oscilloscope with Embedded Sampling Clock Generator”, Dig. IEEE ISSCC, Vol. 1, Session 11, Paper 11.2, February 2002), wherein the sampling clock generator was integrated with 8-sampling circuits such as typically implemented within a laboratory style logic analyzer. The approach is also outlined within Japanese Patent Application 2003/114253.
However, again only sampled signals were generated on-chip and digitization was again performed off-chip within conventional test instrumentation. Prior art digitization has been restricted to simple solutions, such as the single comparator approach of Roberts et al, (G. W. Roberts et al, “A 4-GHz Effective Sample Rate Integrated Test Core for Analog and Mixed Signal Circuits”, IEEE JSSC, Vol. 37, No. 4, pp. 499-514, April 2002) wherein the functional integration was increased, or Roberts and Hafed, (M. M. Hafed and G. W. Roberts, “A 5-Channel Variable Resolution 10 GHz Sampling Rate Coherent Tester/Oscilloscope IC and Associated Test Vehicles”, Proc. IEEE CICC, pp. 621-624, September 2003) where external clock circuits allowed for increased speed of operation.
By extending the circuit with voltage sweeping, the circuit could perform as an on-chip tester with minimum circuit overhead. The voltage sweeping resulting in multiple thresholds such that in conjunction with digital memory digital representations of the signal could be generated. However, common to such prior art comparator based approaches the simplicity was traded off against increased test time, due to requiring the reference voltage to be swept over all possible levels and settle for each “measurement”.
A variation to this is the successive approximation approach to analog-to-digital conversion; see for example the prior art by Price and McIntosh, (C. Price and C. McIntosh, “Successive Approximation Analog-to-Digital Converter” U.S. Pat. No. 6,351,231). This form of ADC having been shown integrated with a sampling circuit by Shepherd and Zheng, (K. L. Shepherd and Y. Zheng, “On-Chip Oscilloscope for Non-Invasive Time-Domain Measurements of Waveforms in Digital Integrated Circuits”, IEEE Trans. On VLSI Systems, Vol. 11, No. 3, pp. 336-344, June 2003).
In mimicking conventional instrumentation, and also simplifyng the BITE circuit block these prior art solutions have relied for the most part on under sampling, see for example FIG. 3 in “Measurement and Prediction of Electromagnetic Emissions from Integrated Circuits” by B. Vrignon et al in Proceedings of IEEE Conference of Electromagnetic Compatibility August 2004. Such under sampling allows the ATE to capture a repetitive high-speed signal with a resolution of a predetermined time interval, which is set by a delay circuit generator, at a relatively low capture rate. Using the multipass approach basically allows the use of the same comparator in many iterations (passes) while varying the DC reference voltage in every new iteration. Hardware complexity is decreased at the expense of increased test time due to the dual-loop system.
Importantly the under sampling approach does not allow the capture of single events, such as occur with one-off error events within ICs or systems measuring nuclear interactions, or even those operating in safety critical or high reliability situations where on-line functional verification is required. In these instances there is no repetition, and the prior art solutions could only provide a solution with the further integration of a recirculating delay line capable of providing the multiple repetitions of the signal being characterized.
It would be advantageous therefore to provide an on-chip high-speed time domain analyzer that supports requirements of DFT and BITE processes but also provides the capability to analyze and characterize signals in real time such as a single error event pass of a signal through the BITE circuit. It would be further advantageous for the solution not to require high speed digital or mixed signal circuits operating faster than the actual IC they are characterizing. Finally the solution should be implementable without significant manufacturing costs and technical requirements that offset the financial benefits of providing the functional analysis and characterization on-chip. Such an on-chip high-speed time domain digital analyzer could function as an oscilloscope, pulse width analyzer, rise time analyzer and even logic analyzer.